Method and device for pulse shaping QPSK signals

ABSTRACT

A baseband shaping device includes a plurality of coefficient memories, each memory having an input address bus, a multiplexor input and a coefficient value output. The device further includes a plurality shift registers, each having an input coupled to a respective one of the coefficient value outputs, a digital to analog clock input and an output. The device further includes a plurality of negative value circuits, each circuit having an input coupled to a respective one of the first shift register outputs and an output, a plurality of multiplexors, each having a first input coupled to a respective one of the first shift register outputs and a second input coupled to a respective one of the output of the plurality of negative value circuits. The device further includes a plurality of second shift registers, and an adder having a plurality of inputs coupled to the plurality of second shift registers.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a U.S. National Stage application under 35 U.S.C.§371 of and claims the benefit of PCT Application No. PCT/US02/12806,filed on Apr. 23, 2002, published in the English language on Nov. 6,2003 as International Publication Number WO 03/092233 A1, which arehereby incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates generally to modulation of RF carrier signals andmore particularly to systems and techniques to shape baseband signalsfor QPSK modulation.

BACKGROUND OF THE INVENTION

In communications applications, it is often desirable to use multiphasemodulation techniques to increase bandwidth efficiency in telephone andsatellite data communications to transmit binary data as multiple bitsymbols and in particular quadrature phase shift keying (QPSK)modulation. However, when using QPSK modulation in data communicationsterminals, there is often a requirement to limit the spectralcharacteristics of the radio frequency (RF) modulated signal to reduceintersymbol interference. As is known in the art there are severalfiltering techniques to shape a baseband signal, wherein a digitalsignal which is separated into two data streams, an in-phase signal anda quadrature phase signal, also referred to as the quadrature signal,before RF modulation.

Conventional techniques for implementing filters include square rootraised cosine (SRRC) filters which provide outputs having data samplesgenerated at a frequency F_(da) which is equivalent to a digital toanalog converter clock rate. Typical filter circuits include a tappeddelay line filter having filter taps spaced at 1/(F_(da)) in time.Inputs bits come in at a symbol rate (Rs). Typically the filtercoefficients are chosen so that a response to an impulse signal is theSRRC characteristic waveform in the time domain. To provide a basebandsignal for modulating a radio frequency (RF) carrier, an impulse signalis input into the filter once per symbol.

This impulse signal consists of the value +1 (for a data “0”) or −1 (fora data “1”) followed by several samples of value 0. In a typical filtermost of the multipliers are multiplying their coefficient by the value0, and are therefore not being used. This adds digital logic that is notnecessarily required.

In communication applications, low cost and compact size are importantconsiderations. Digital filters such as those described above are oftenimplemented as field programmable gate arrays (FPGAs) and applicationspecific integrated circuits (ASICs).

Reducing the required circuitry to implement a particular filter canreduce the cost and size of the filter.

It would, therefore, be desirable to reduce the size and cost of thedigital logic for implementing the baseband filter including reducingthe volume of circuitry dedicated to the storage of coefficient valuesfor producing the filtered baseband signal.

SUMMARY OF THE INVENTION

In accordance with the present invention, a device includes a pluralityof coefficient memories, and each memory having an input address bus, amultiplexor input and a coefficient value output The device furtherincludes a plurality of first shift registers, each having an inputcoupled to a respective one of the coefficient value outputs, a digitalto analog (D/A) clock input and an output. The device further includes aplurality of negative value circuits, each circuit having an inputcoupled to a respective one of the first shift register outputs and anoutput, a plurality of 2:1 multiplexors, each multiplexor having a firstinput coupled to a respective one of the first shift register outputsand a second input coupled to a respective one of the output of theplurality of negative value circuits. The device further includes aplurality of second shift registers, each having an input coupled to arespective one of the outputs of the plurality of 2:1 multiplexors, adigital to analog (D/A) clock input and an output, and an adder having aplurality of inputs coupled to respective ones of the plurality ofsecond shift registers. With such an arrangement, the digital logicimplementing the filter and the volume of circuitry dedicated to thestorage of coefficient values for producing the filtered baseband signalis reduced.

In accordance with a further aspect of the present invention, a methodfor shaping a baseband signal includes providing a plurality ofcoefficient memories, each coefficient memory having a plurality ofcoefficients values, each of the plurality of coefficient valuesrepresenting a filter response waveform value, and determining acoefficient memory address for each of the coefficient memories. Themethod further includes addressing each of the plurality of coefficientmemories, retrieving an addressed coefficient value from each of theplurality of coefficient memories, providing a negative value for eachof the retrieved coefficient values, selecting in response to thebaseband signal, one of the retrieved value and the negative value,summing the selected value for each coefficient for providing a shapedsignal. With such a technique, an efficient implementation of squareroot raised cosine filter is provided having a reduced storagerequirement for the filter coefficients.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of this invention, as well as the inventionitself, may be more fully understood from the following description ofthe drawings in which:

FIG. 1 is a block diagram of a data path processing circuit of a QPSKmodulator according to the invention;

FIGS. 2A-2D are schematics of a baseband shaping circuit according tothe invention;

FIG. 2E is a schematic of one stage of the baseband shaping circuit ofFIGS. 2A-2D;

FIGS. 3A-3C are schematics of a baseband shaping circuit according to afurther aspect the invention;

FIG. 3D is a schematic of one stage of the baseband shaping circuit ofFIG. 3; and

FIGS. 4A-4D are schematics of a baseband shaping circuit according to astill further aspect of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Before providing a detailed description of the invention, it may behelpful to define some of the terms used in the description. As usedherein, two's complement logic coefficients and logic blocks refer to anegative representation of a digital signal value and in particular thenegative value of a filter coefficient. As is known, conventional logicbuilding blocks for adders use two's complement arithmetic. It will beappreciated by those of ordinary skill in the art that otherrepresentations of the negative coefficient such as offset binary orsigned magnitude representations can be used instead of the two'scomplement representation along with corresponding negative value logiccircuits.

For purposes of the present invention, as used herein the term“coefficient” refers generally to a factor which is used to multiply aninput bit stream for implementing a specific filter. A coefficientincludes a plurality of coefficient values which are discrete digitalsamples representing filter response waveform values of a particularfilter waveform. For example, C0 represent the first coefficient to beused in a specific filter. Coefficient values C0 ₀-C0 _(N) representdiscrete samples of the coefficient, and these values are stored in acoefficient memory. The coefficient values are addressed by thecoefficient, here C0, and the sample number 0 to N. N is determined bythe relationship between the symbol rate and the D/A converter clockrate. For example, if the D/A clock rate is sixteen times the symbolrate, then N would be equal to fifteen and there would be sixteensamples per coefficient.

One inventive concept of this present invention resulted from therealization that because of the symmetry of the filter coefficients thestorage requirements for coefficient values could be reduced. By storingthe combined coefficient values with the capability to take the negativevalue, for example the two's complement, of the coefficient values,coefficients are combined to reduce, for example by one-half, the amountof memory required to store baseband signal shaping filter values.Address generation circuitry is provided to address the coefficientmemories to provide the coefficient values in the proper order inresponse to the baseband signals.

Now referring to FIG. 1, an exemplary QPSK modulator 100 according tothe invention includes a transmit data interface 102 coupled to anin-phase baseband bit shaping circuit 104I and a quadrature baseband bitshaping circuit 104Q (generally referred to as baseband bit shapingcircuits 104). The baseband bit shaping circuits 104I and 104Q eachinclude an input to receive a serial bit stream provided by a pluralityof in-phase data symbols and quadrature data symbols respectively. Thebaseband bit shaping circuits 104I and 104Q each receive timing andcontrol signals from timing and control circuit 118 including a masterclock signal, a digital to analog converter (D/A) clock signal and asymbol (SYM) clock input, and each circuit 104I and 104Q includes a D/Aoutput. The QPSK modulator 100 further includes a pair of digital toanalog converters (D/A) 106 each coupled to one of the respectivebaseband bit shaping circuits 104I and 104Q D/A outputs. The D/As arecoupled to an RF modulator 108 which is coupled to an upconvertor 110.The upconvertor 110 is coupled to a power amplifier 112 which is coupledto a diplexer 114 which is coupled to an antenna 116 in a known manner.

In one embodiment, the QPSK modulator 100 including portions of thetransmit data interface 102 and the baseband bit shaping circuits 104are implemented in a field programmable gate array (FPGA) in a satellitecommunications modulator. The transmit data interface 102 and thebaseband bit shaping circuits 104 process the data (grouped as symbols)and provide the processed signals as discrete digital waveform values tothe dual D/A's 106.

The transmit data interface 102 provides serial data to the baseband bitshaping circuits 104 to provide the in phase and quadrature waveforms tomodulate a radio frequency carrier. In one embodiment the transmit datainterface 102 selects between a synchronous serial interface orasynchronous parallel interface for transmit data. Utilizing thesynchronous serial interface, the external transmit circuitry providestwo bits of each data symbol (multi-bit binary data), including one bitI and one bit Q on each rising edge of the clock symbol clock providedby the timing and control circuit 118. Utilizing an asynchronousparallel interface, data to be transmitted is delivered as symbols tothe transmit data interface 102 through the byte wide control/status busand buffered in a first-in first-out register (FIFO) (not shown). TheFIFO, which is implemented as part of the transmit data interface 102,allows an external processor (not shown) to send multiple bytes ofmessage data to the transmit data interface 102 prior to transmission.The byte wide output of the FIFO is then parallel to serial convertedinto two bit symbols for QPSK modulation on each rising edge of theclock symbol clock. It will be appreciated that the exemplary embodimentof FIG. 1 illustrates one of several possible configurations for theQPSK modulation 100.

The baseband bit shaping circuits 104, as described further inconnection with FIGS. 2A-4D, shapes the serial data supplied by thetransmit data interface and provides the digital waveform representingthe filtered baseband signals to the digital to analog converters 106.The digital to analog converters 106 provide an analog waveform to theRF modulator 108 to modulate an RF carrier signal which is converted toa higher frequency by the upconvertor 110. The power amplifier 112amplifies the upconverted signal which is then received by the diplexer114. In a transmit mode, the diplexer 114 directs the amplifiedupconverted signal to the antenna for transmission.

Now referring to FIGS. 2A-2D, an in-phase baseband bit shaping circuit200I, similar to the baseband bit shaping circuit 104I (FIG. 1),includes a tapped delay line 202I having a plurality of delay elements203 and a plurality of taps 205 and coupled to an in-phase data bitstream. The circuit 200I further includes a plurality of stages 204a-204 n (generally referred to as stage 204), each stage coupled to acorresponding tap 205 of the delay line 202I. Each stage 204 has anoutput coupled to a corresponding input of an adder 206I which has anoutput coupled to an input of a scaler circuit 208I. The scaler 208I hasan output which is coupled to an in-phase D/A (not shown). A quadraturebaseband bit shaping circuit 200Q includes a similar arrangement ofcircuits.

The quadrature baseband bit shaping circuit 200Q, similar to thebaseband bit shaping circuit 104Q (FIG. 1), includes a tapped delay line202Q having a plurality of delay elements 213 and a plurality of taps215 and coupled to an quadrature data bit stream. The circuit 200Qfurther includes a plurality of stages 214 a-214 n (generally referredto as stage 214), each stage coupled to a corresponding tap 215 of thedelay line 202Q. Each stage 214 has an output coupled to a correspondinginput of an adder 206Q which has an output coupled to an input of ascaler circuit 208Q. The scaler 208Q has an output which is coupled toan in-phase D/A (not shown).

Now referring to FIG. 2E, each stage 204 of the baseband shaping circuit200I of FIGS. 2A-2D includes a coefficient memory 220 coupled to acoefficient address generator 228 through an address bus 230. Thecoefficient memory 220 includes a clock input signal 232 coupled to thecoefficient address generator 228. The coefficient memory 220 includescoefficient memory output 222 which is coupled to a first input of amultiplexor 226. The coefficient memory is also coupled to a negativevalue circuit 224, here, a two's complement circuit to provide anegative value of the coefficient memory output 222 to a second input ofthe multiplexor 226. The multiplexor 226 includes a select input 234coupled to the corresponding tap 205 of the delay line 202 (FIGS. 2A-2D)and an output 240. It should be appreciated a similar circuit is usedfor each stage 214 of circuit 200Q of FIGS. 2A-2D.

Referring to FIGS. 2A-2E, in operation, the baseband bit shapingcircuits 200 provide the digital signal processing necessary forspectral confinement of the modulated output carrier. The coefficientaddress generator 228 is clocked by the D/A clock to provide coefficientaddresses for addressing the coefficient memories to provide waveformsamples at the D/A clock frequency. In one embodiment providing QPSKmodulation, the baseband bit shaping waveform is a square root raisedcosine (SRRC) waveform with various roll-off factors. In one embodimentthe roll-off factor is selectable at 25%, 35%, 50% and 70%. The roll-offfactor is held constant during a single transmission of a series ofsymbols which is referred to as a burst. Different sets of coefficientvalues are stored in the coefficient memory 220 for each roll-offfactor. It will be appreciated by those of ordinary skill in the artthat several memory arrangements can be provided including loadingdifferent sets of coefficient values into the memory 220 when differentroll-off factors are selected or having a single larger memory with adifferent section for each set of coefficient values. After a particularset of coefficient memory values has been selected for a particularburst, the coefficient address generator 228 addresses the selected setof coefficient values in the coefficient memory 220. A particularroll-off factor is selected for a particular burst as a function oftransmission bandwidth, and transmitter power amplifier 112 (FIG. 1),and receiver complexity. Lower roll-off factors (e.g.; 25%) use less ofthe link bandwidth which is advantageous because the lower roll-offfactor allows more of the limited bandwidth available to be used byother links. However, the lower-roll off factor causes a higher ratio ofpeak transmitted power to average transmitted power. The higher ratiorequires the transmitter power amplifier to have a higher peak powercapability, which makes it more complex. Also, the lower roll-off factorrequires a longer matched filter in the receiver which will receive thetransmitted waveform. This makes the receiver more complex. Higherroll-off factors (e.g.; 70%) use more of the link bandwidth which isdisadvantageous because the higher factor allows less of the limitedbandwidth available to be used by other links. But, the higher roll-offfactor causes a lower ratio of peak transmitted power to averagetransmitted power. The lower ratio allows the transmitter poweramplifier have a lower peak power capability, which makes it lesscomplex. The lower roll-off factor requires a shorter matched filter inthe receiver which will receive the transmitted waveform. This makes thereceiver less complex. Providing the flexibility of switching betweencoefficient memories can require additional storage capacity, but thetotal storage requirements are reduced by the present invention. It willbe appreciated by those of ordinary skill in the art, that once thecoefficients are provided according to the present invention, memorybanks or other arrangements of the coefficients corresponding todifferent roll-off factors can be selected using known techniques andthe tradeoffs described above.

The stage 204I operates as one tap of a digital filter having a tappeddelay line structure which is, here, eight symbols in length with apredetermined set of coefficients for each tap based on the desiredroll-off factor. The data is multiplied by the coefficients, with theresults from each tap summed in adder 206I, scaled by the scaler circuit208I and then used to drive the D/A converters 106 (FIG. 1). Thisstructure is similar for both the I and Q channels. The stage 204I is aninterpolating filter tap, so for every symbol processed by the filter,there are N_(INT) samples in the waveform provided to the D/A converter106,

where

-   -   _(INT) refers to interpolation; and    -   N_(INT)=(D/A Clock Rate)/(Symbol Rate);    -   N_(INT)=N+1; and    -   N refers to the sample number described above.        The symbol bit coefficients are “multiplied” by changing or not        changing their sign, according to the value (+1 or −1) of each        symbol. In one embodiment using twos complement arithmetic, this        operation corresponds to using the coefficient value or its “two        complement” value. Note that each symbol multiplies each        coefficient only once. The effect is the same as if the filter        was an 8 N_(INT) long tapped delay line filter (for an 8-tap        filter), with impulses (+1 or −1 followed by [N_(INT)−1] 0s) as        the input to the tapped delay line.

In some analog implementations of the filter, instead of impulses (+1 or−1 followed by [N_(INT)−1] 0s) input into the tapped delay line, the +1or −1 is repeated N_(INT) times. In the second case (repetition), thetransmitted spectrum of the waveform would be multiplied by a[sine(fx)/(fx)] function, which is defined as “sinc(fx).” Here, f is thefrequency offset from the carrier and x is a factor which depends on thesymbol rate. To compensate for this, the coefficients would be computedfrom the inverse Fourier transform of the desired spectrum after it hasbeen multiplied by [1/sinc(fx)]=[(fx)/sine(fx)]. This is a so-called“inverse sinc function compensation.” Since the present inventionimplements the mathematical equivalent of impulses, this inverse sincfunction compensation is not required.

Now referring to FIGS. 3A-3C, a schematic of a baseband shaping circuit300 according to a further aspect the invention includes tapped delaylines 302I and 302Q similar to the delay line 202I and 202Q of FIGS.2A-2D respectively. The tapped delay lines 302I and 302Q are coupled toan in-phase data bit stream (I Data) and a quadrature data bit stream (QData) respectively. The circuit 300 further includes a plurality ofstages 304 a-304 n, each stage coupled to a corresponding tap of delayline 302I and 302Q. Each stage 304 has outputs coupled to acorresponding input of an adder/scaler circuit 306I and of 306Qrespectively. The adder/scaler 306I and 306Q have outputs which arecoupled to an in-phase D/A (not shown) and quadrature D/A (not shown)respectively. The circuit 300 includes a common coefficient addressgenerator 308 having a clock input 310 which is coupled to the D/Asample clock, and an up address output 312 coupled to the coefficientmemories of a first portion of the stages 304 and a down address output314 coupled to the coefficient memories of a second portion of thestages 304. A first plurality of stages 304 is coupled to an up addressbus 312 coupled to the coefficient address generator 308 which isclocked by the D/A clock. The coefficient address generator 308 is alsocoupled to a down address bus 314 coupled to a second plurality of thestages 304. One inventive feature of the baseband shaping circuit 300takes advantage of the fact that the same coefficients are used for eachcorresponding tap in the I and Q channels, thus allowing logic (e.g.address generators and multiplexors) and coefficient memories to beshared for both the I and Q channels.

Now referring to FIG. 3D, each stage 304 of the baseband shaping circuit300 of FIGS. 3A-3C includes a coefficient memory 320 coupled to thecoefficient address generator 308 by address bus 330. The coefficientmemory 320 is coupled by the address bus 330 to a corresponding one ofthe up address bus 312 or the down address bus 314 as necessary. Thecoefficient memory 320 is coupled to a coefficient memory outputregister 322 which is coupled to a first input of a multiplexor 326I anda first input of a multiplexor 326Q. The coefficient memory 320 is alsocoupled to a negative value circuit 324, here, a two's complementcircuit to provide a negative value of the coefficient memory output 322to a second input of the multiplexor 326I and a second input of themultiplexor 326Q. The multiplexor 326I includes a select input 334Icoupled to the corresponding tap of the delay line 302I (FIGS. 3A-3C)and an output 340I. The multiplexor 326Q each includes a select input334Q coupled to the corresponding tap of the delay line 302Q (FIGS.3A-3C) and an output 340Q. In this embodiment of the shaping circuit300, the address generator 308 provides an incrementing address, upaddress output 312 (starting at 0 and increasing) and a decrementingaddress, down address output 314 (starting at the maximum value anddecreasing) to address the coefficient memories 320, taking advantage ofthe symmetry of the coefficients but reverse ordering to provide thesymmetrically shaped waveform.

Stage 304 operates in a similar manner as stage 204 (described above inconjunction with FIG. 2E) with the additional feature of providing theaddressed coefficient values and the negative coefficient values to bothI data stream and the Q data stream at a rate clocked by the D/A clock.

Now referring to FIGS. 4A-4D, an exemplary baseband shaping circuit 400according to a still further aspect of the invention provides aninventive coefficient storage technique. Circuit 400 includes acoefficient address generator 416 providing an address bus and aplurality of multiplexor most significant bit (MSB) outputs coupled to amultiplexor (MSB) input of a corresponding one of a plurality ofcoefficient memories 420 a-420 n (generally referred to as coefficientmemory 420). Outputs of the plurality of coefficient memories 420 a-420n are coupled to a corresponding plurality of stages 418 a-418 n (eachstage generally referred to as stage 418) each having an in phase (I)output and a quadrature (Q) output. The in-phase (I) outputs are coupledto corresponding stages of adders 450I and 452I having an output coupledto a scale and format converter 470I which has an output coupled to anID/A converter (not shown). The quadrature (Q) outputs are coupled tocorresponding stages of adders 450Q and 452Q having an output coupled toa scale and format converter 470Q which has an output coupled to a Q D/Aconverter (not shown).

The coefficient address generator 416 includes a plurality ofmultiplexors 402 ₀₇-402 ₃₄ (generally referred to as multiplexors 402),each of the multiplexors 402 having I and Q inputs coupled tocorresponding outputs of a two stage I Channel input data (symbol) shiftregister 440I and a two stage Q Channel input data (symbol) shiftregister 440Q. The two stage shift registers 44OI and 44OQ include ashift registers 442I, 444I and 442Q, 444Q respectively coupled in seriesand in parallel to provide I channel data and Q channel data eachclocked by both the symbol clock and the D/A clock as shown in FIG. 4C.The overall operation and signal flow of the circuit 400 starts with theI channel and Q channel shift registers 440I and 440Q respectively inFIG. 4C. The eight individual registers 442Ia-442Ig and 442Qa-442Qg,respectively for each channel represent the eight taps of the delay linein the filter. Symbol data is clocked into the “delay line” at thesymbol clock rate. There are multiple D/A clock cycles for each symbolclock cycle, here a minimum of two D/A clock cycles up to a maximum ofsixty-four. The outputs of these registers 442 provide the inputs to themultiplexors 402 in the address generator 416 of FIGS. 4A-4B and remainconstant for the entire symbol period. The same coefficient memory 420is used to generate coefficients for both the I and Q channels duringeach D/A clock cycle. In the first half of the D/A clock cycle, the Ichannel coefficients are generated, then in the second half of the D/Aclock cycle the Q channel coefficients are generated. The outputs ofthese registers 442 also provide inputs to corresponding inputs ofregisters 444Ia-444Ig and 444Qa-444Qg (collectively referred to asregisters 444). The outputs of registers 444 provide outputs I0D-I7D,Q0D-Q7D as inputs to a digital logic circuit implementing the truthtable shown in Table II which provides the SELI07-SELQ07, SELI16,SELQ16, etc. The I0D-I7D, Q0D-Q7D output signals are the I0-I7, Q0-Q7signals delayed one D/A clock cycle to provide the correct timingrelationship with respect to the coefficient memory 420 output.

Now referring to one of the four combined coefficient set C0 and C7,during the first half of the D/A clock cycle the I0 and I7 outputs ofregisters 442 a and 442 g are selected by the state of SEL I/Q and arepassed through multiplexor 402 ₀₇ to the inputs of XOR gate 404 ₀₇.Likewise in the second half of the D/A clock cycle the Q0 & Q7 outputsof registers 442 are selected and passed through the multiplexor 402 ₀₇to the XOR gate 404 ₀₇. The output of the XOR gate 404 ₀₇ forms the mostsignificant bit of the address into the coefficient memory as describedin Table I below. Referring now to the I channel, the XOR gatedetermines whether the symbol bits I0 & I7 have the same value (samevalue means same sign positive or negative). If symbol bits I0 & I7 havethe same value, the coefficient value to be selected from thecoefficient memories 420 a is the I0+I7 coefficient. If symbol bits I0 &I7 have different values (opposite signs), the I0−I7 coefficient isselected. The desired coefficient is then accessed in the coefficientmemories 420 a and stored in the register 430 on the rising edge of theD/A clock. The registers 430 are shown in FIG. 4A having the risingclock edge storage and positive (digital “1”) enable (EN). When SEL I/Qis high (the first half D/A clock cycle) and providing a rising clockedge, the I coefficient is stored in register 430I. When SEL I/Q is low(the second half D/A clock cycle) and providing a falling clock edge(both clock and EN inputs to register 430Q are inverted), the Qcoefficient is stored in register 430Q. In this manner, both the I and Qcoefficients are accessed in a single D/A clock cycle.

TABLE I Modified Coefficient Memory Contents NEW MEMORY ADDRESS ADDRESSADDRESS Out of MSB07 plus Out of NEW XOR Array New MEMORY Adder 408PAIRINGS SYMMETRY PAIRINGS 412 Address CONTENT 1111 C0₀ & C7₁₅ C0₀ = C7₀C0₀ & C0₁₅ 000 0000 C0₀ + C0₁₅ 0000 C0₁₅ & C7₀ C0₁₅ = C7₁₅ C0₁₅ & C0₀000 1000 C0₀ − C0₁₅ 1110 C0₁ & C7₁₄ C0₁ = C7₁ C0₁ & C0₁₄ 001 0001 C0₁ +C0₁₄ 0001 C0₁₄ & C7₁ C0₁₄ = C7₁₄ C0₁₄ & C0₁ 001 1001 C0₁ − C0₁₄ 1101 C0₂& C7₁₃ C0₂ = C7₂ C0₂ & C0₁₃ 010 0010 C0₂ + C0₁₃ 0010 C0₁₃ & C7₂ C0₁₃ =C7₁₃ C0₁₃ & C0₂ 010 1010 C0₂ − C0₁₃ 1100 C0₃ & C7₁₂ C0₃ = C7₃ C0₃ & C0₁₂011 0011 C0₃ + C0₁₂ 0011 C0₁₂ & C7₃ C0₁₂ = C7₁₂ C0₁₂ & C0₃ 011 1011 C0₃− C0₁₂ 1011 C0₄ & C7₁₁ C0₄ = C7₄ C0₄ & C0₁₁ 100 0100 C0₄ + C0₁₁ 0100C0₁₁ & C7₄ C0₁₁ = C7₁₁ C0₁₁ & C0₄ 100 1100 C0₄ − C0₁₁ 1010 C0₅ & C7₁₀C0₅ = C7₅ C0₅ & C0₁₀ 101 0101 C0₅ + C0₁₀ 0101 C0₁₀ & C7₅ C0₁₀ = C7₁₀C0₁₀ & C0₅ 101 1101 C0₅ − C0₁₀ 1001 C0₆ & C7₉ C0₆ = C7₆ C0₆ & C0₉ 1100110 C0₆ + C0₉ 0110 C0₉ & C7₆ C0₉ = C7₉ C0₉ & C0₆ 110 1110 C0₆ − C0₉1000 C0₇ & C7₈ C0₇ = C7₇ C0₇ & C0₈ 111 0111 C0₇ + C0₈ 0111 C0₈ & C7₇ C0₈= C7₈ C0₈ & C0₇ 111 1111 C0₇ − C0₈

Signal 434I SELI07 is generated by logic implementing a truth table asdescribed in Table II below. In response to signal 434I, the multiplexor426 provides true output of the register 430 for the first half of thesamples for the current symbol (e.g. if there are eight D/A samples persymbol, the first half would be samples 0, 1, 2 and 3 and the secondhalf would be 4, 5, 6 and 7). The multiplexor 426 provides the negative(two's complement) output 424 of the register 430 for the second half ofthe samples. Depending on the output of the XOR gate 404 ₀₇, thecoefficient memory 420 provides either the coefficient value I0+I7 orI0−I7. The signal 434I SELI07 then selectively provides the tworemaining coefficient combinations —(I0+I7) or (I7−I0). The addresscounter most significant bit (ACCMSB) signal changes from a binarydigital logic “1” to a “0” when there is a transition from the firsthalf of the samples for a symbol to the second half of the samples. Theoutput is stored in registers 432 which provide the coefficient valuesas input to the adder chains 460 of FIG. 4D.

It should be noted that only four inputs are added for each channel eventhough there are eight taps to the filter, because symmetric coefficientpairs are combined in the programming of the coefficient memories 420.An additional point to note about the address generator 416 is that italways counts up in binary to the same “rollover” point with six bits ofcount (six bits provides counts from zero to sixty-three then rolls overto zero and starts again). The count increment stored in register 406 ismodified based on the number of D/A samples per symbol (e.g. if eightsamples per symbol are desired, the number eight is stored in register406, if four samples per symbol are desired, the number sixteen isstored in register 406.

Each of the multiplexors 402 has two outputs which are coupled to twoinputs of an exclusive or logic (XOR) gate 404 and the output of thelogic gate 404 is coupled to the multiplexor (MSB) input of thecorresponding coefficient memory 420. The coefficient address generator416 further includes a register 406 coupled to a modulatorcontrol/status bus and having an output coupled to an input of amultiple bit adder 408, here a six bit adder. The adder 408 has anoutput coupled to a register 410 which has a clock input coupled to theD/A clock. The register 410 has a first output which is the sum producedby the adder and each of the lower bits, here the lower five bits, whichare coupled to a first input of an XOR gate array 412. The register 410has a second output which is the most significant bit produced by theadder 408 and is coupled to a second input of the XOR gate array 412 andto a second input of the adder 408. The XOR gate array 412 has amultiple bit output which is coupled to the address bus input of thecorresponding coefficient memory 420. Each lower order bit in the outputof adder 408 is XOR'ed with the most significant bit produced by theadder 408. Equivalently in Table I, the XOR gate array 412 converts theADDRESS to the corresponding NEW ADDRESS, which is combined, examplewith the output of the XOR gate 404 ₀₇ to provide the MEMORY ADDRESS foraddressing the coefficient memory 420.

Each stage 418, which is similar to stage 304 (FIGS. 3A-3C), includes apair of registers 430I and 430Q, each register having a coefficientinput coupled to a corresponding coefficient memory 420, a clock inputcoupled to the D/A clock and an enable input coupled to a SEL IQ. Theclock input to register 430Q is inverted by an inverter 427. Each of thepair of registers 430I and 430Q has an output coupled to a first inputof a multiplexor 426I and a multiplexor 426Q respectively. The output ofregisters 430I and 430Q is also coupled to negative value circuits 424,here, two's complement circuits to provide a negative value of thecoefficient in registers 430I and 430Q as outputs to respective secondinputs of the multiplexor 426I and the multiplexor 426Q. The multiplexor426I includes a select input 434I coupled to a SEL I/Q XY signal, andthe multiplexor 426I has a COEFF I XY output. The multiplexor 426Q eachincludes a select input 434Q coupled to a SEL I/Q XY signal and a COEFFQ XY output.

A register 414 of the coefficient address generator 416 has an inputcoupled to the most significant bit produced by the adder 408 and aclock input coupled to the D/A clock, and provides a signal ACCMSBD tologic implementing a truth table (described below in more detail inconjunction with Table II) to provide the SEL I/Q XY signals.

The first adder stage 450I includes a plurality of adders 460 having apair of input coupled to the corresponding pair of COEFF I/Q XY outputsfrom stage 418, and an output coupled to a pipelined register 462. Theregister 462 has an output coupled to an input of an adder 460 in asecond adder stage 452I. It will be appreciated by those of ordinaryskill in the art that the number and configuration of the adder stages450I and 452I can be provided in several equivalent arrangements.

In a similar manner, the first adder stage 450Q includes a plurality ofadders 460 having a pair of input coupled to the corresponding pair ofCOEFF I/Q XY outputs from stage 418, and an output coupled to apipelined register 462. The register 462 has an output coupled to aninput of an adder 460 in a second adder stage 452Q. It will beappreciated by those of ordinary skill in the art that the number andconfiguration of the adder stages 450Q and 452Q can be provided inseveral equivalent arrangements. After the adder stages 450I, 452I 450Qand 452Q sum the pipelined coefficient values, the respective scale andformat converters 470I and 470Q scale and format the waveform outputsamples for D/A conversion.

Further improvement in reducing coefficient storage requirements isachieved by some additional complexity in the circuit 400. In anembodiment, having for example eight coefficients corresponding to eightfilter taps, the circuit 400 takes advantage of the symmetry in thecoefficients (i.e. the same coefficient set is used for C0 and C7, C1and C6, C2 and C5, C3 and C4). It should be noted that some coefficientsare accessed in reverse order to provide the trailing portion of thefilter waveform. Further combining the coefficient pairs by storing thesums and differences in the coefficient memories 420 rather than theindividual coefficients cuts coefficient storage requirements in halfand an additional adder stage can be eliminated. Table I illustratesthis coefficient storage approach for a sixteen coefficient values foreach of eight filter tap coefficients.

In operation the coefficient memory addresses are generated by thecoefficient address generator 416 operating as a counter that counts thedesired number of D/A samples per symbol (here up to the maximum numberof 64 which is equal to the size of coefficient memory 420). Theincrement of the count varies based on the number of samples per symboldivided into the maximum number of 64. Register 406 is loaded with theselected increment. Therefore, for a given transmission rate generatingD/A samples at a rate of 16 samples per symbol, the counter wouldincrement by 4 each D/A clock cycle, thereby using every fourthcoefficient value in the coefficient memory 420. The address counter isimplemented as an adder/accumulator where the increment is provided asinput to the accumulator and the accumulated “sum” forms the actualaddress to the coefficient memory 420. The baseband shaping circuit 400,supports more than one transmission rate which is related to powerconsumption. The transmission rate is selectable via a combination ofthe selectable frequency of the D/A clock and the increment valueprogrammed into register 406.

The sum and difference waveform values represented by the positivecoefficient values (also referred to as the true values) and the two'scomplement (negative) coefficient values are selected by themultiplexors 426 based upon the value of the data symbols at the 8 tapsof the filter shift registers 442 (registers that are clocked on thesymbol clock, not the D/A clock) and the current count of the D/A samplenumber (i.e. if there are 64 samples per symbol, which of the 64 samplesis currently selected).

In operation the baseband shaping circuit 400 uses the symbol data bitsas a positive or negative multiplier (i.e. data symbol bit “1”=+1, datasymbol bit “0”=−1) to alter the sign of the coefficient for each of thetaps of the filter, here eight taps. For a given coefficient pair set(i.e. two taps out of the filter, e.g. C0 and C7), upon multiplicationby the symbol bit, one of the following quantities is formed: C0+C7;C0−C7; C7−C0; or −C0−C7, and, since −C0−C7=−(C0+C7) and C 7−C0=−(C0−C7),only two quantities need to be stored in memory (C0+C7 and C0−C7) withthe capability to take the negative value, here the two's complement, ofthe coefficient in accordance with the present invention. Thedetermination of when to negate the coefficient value is based on thetwo data bits from the tapped delay line, here two stage I/Q Channelinput data (symbol) shift registers 440, and the most significant bit ofthe coefficient address generator 416 since this bit indicates the needfor reverse order pairing as shown in the New Pairings column of TableI.

The coefficient address generator 416 provides a means to step throughthe coefficient memory in increments of 1, 2, 4, 8, 16 or 32, whichcorresponds to 64, 32, 16, 8, 4, 2 D/A samples per symbol. The mostsignificant bit (MSB) of the address counter adder 408 is used to invertthe rest of the counter address output bits in the XOR array 412 to takeadvantage of the symmetry of the coefficients as seen at mid-symbol(i.e. if required to generate 16 D/A samples per symbol, the first 8coefficients will be a mirror image of the last eight as referenced tomid-symbol as seen in reference to the New Pairings column in Table I).

The output of the XOR gate 404 ₀₇, the signal MSB07 is simply an XOR ofthe two data symbol bits from the two taps of the filter shift registers442 combined to operate on the given coefficient memory (C0 & C7, C1 &C6, C2 & C5, C3 & C4), here for example C0 & C7. This XOR outputindicates whether the bits are the same or different. If they are thesame, this means the coefficient to be used will be either C0+C7 or−(C0+C7). If they are different, this means the coefficient to be usedwill be either C0−C7 or −(C0−C7) (note only C0+C7 and C0−C7 are actuallystored in memory and the negative of these coefficient values is createdwith digital logic.

The truth table as shown in Table II and implemented in the FPGA ofcircuit 400, provides the SEL I/Q XY signal,

-   -   where I/Q indicates which register 430I or 430Q receives the        coefficient value; and    -   XY indicates the coefficient pair.

TABLE II MUX SELECTS SEL I/Q XY TRUTH TABLE ACCMSBD I/Q XD I/Q YD SELI/Q XY 0 0 0 Negative Coefficient 0 0 0 Negative Coefficient 0 1 0Positive Coefficient 0 1 1 Positive Coefficient 1 0 0 NegativeCoefficient 1 0 1 Positive Coefficient 1 1 0 Negative Coefficient 1 1 1Positive Coefficient

The truth table, Table II includes the logical relationship between themost significant bit of the address counter (adder/accumulator) and thetwo data symbol bits to generate the SELI/Q XY signals (e.g. SELI07,SELQ07) which determines whether the positive or negative value of thecoefficient memory value (i.e. C0+C7 or −(C0+C7)) is provided as outputto the adder stages 450 and 452.

In certain embodiments, depending upon the speed of the device family(e.g. FPGA or ASIC devices) used to implement the baseband shapingcircuit 400 and the desired transmission rate, the mathematicalprocessing of a given input symbol cannot be performed in a singlesystem clock cycle (i.e. symbol data input to first D/A sample out),therefore, the process is divided into a number of steps, each performedin a single clock cycle. The implementation is then “pipelined” wherethe registers 462 are placed at the output of each processing step toresynchronize the outputs to the system clock. The result is a fixeddelay or latency between input symbol and the first output D/A sample atthe start of a transmission burst but then all other D/A samples followin sequence on consecutive clock cycles as provided by input data(symbol) shift registers 440I and 440Q which are similarly pipelined.

For clarity, Table I represents only the C0 and C7 coefficient setpairing. A similar pairing exists the remaining coefficient sets C1 &C6, C2 & C5 and C3 & C4. For example, replace C0 with C1 and C7 with C6to provide the table coefficient set pairing for C1 and C6 and so forth.For a given coefficient pair set, upon multiplication by the symbol bit,the adder forms one of the following quantities: C0+C7; C0−C7; C7−C0; or−C0−C7.

In addition, since −C0−C7=−(C0+C7) and C7−C0=−(C0−C7), only twoquantities, for example, (C0+C7) and −(C0−C7) need to be stored inmemory with the capability to provide the negative value. Thedetermination of when to negate the coefficient value, here using thenegative value circuit 424 is based on the two data bits from the tappeddelay line and the most significant bit of the base address generatorsince this bit indicates the need for reverse order pairing as shown inthe New Pairings column of Table I.

As indicated in Table I, each coefficient, for example, C0 comprises aset of coefficient values C0 ₀−C0 _(n) where n equals the number ofsamples to be provided at the D/A clock rate for a given symbol period.The values in Table I are provided for n=15 which provides 16 samplesper symbol period.

As the data symbols are entered into the input data (symbol) shiftregister 440I and 440Q, the circuit 400 provides as many as 64 discretesamples per symbol. Note that Table I provides an example having sixteensamples per symbol for clarity. The pairings column of Table I representthe values used from the two coefficients C0 and C7 to produce any ofthe 16 discrete output samples. There are similar pairings of C1 withC6, C2 with C5 and C3 with C4. The symmetry column of Table Iillustrates the symmetry in the coefficients for C0 and C7. The samesymmetry applies to C1 with C6, C2 with C5 and C3 with C4. The NewPairings column of Table I substitutes the C0 value for the C7 value totranslate the coefficient values to a single set of 16 values, in thiscase the C0 values. The same pairing applies to C1 with C6, C2 with C5and C3 with C4. The new address column of Table I shows that based onthe new pairings, the initially required address range shown in thefirst column is reduced by a factor of two since the coefficient valuesin the new pairings column repeat (i.e. each pairing is used twice).

The memory address and memory content columns of Table I represent thephysical address scheme implemented in circuit 400 and contents of thememory which provides two of the possible four combinations of the twocoefficient values (C0x+C0y or C0x−C0y). The remaining two possiblevalues are obtained by taking negative value, here for example the two'scomplement of the values (−C0x−C0y or −C0x+C0y, respectively).

The logic as shown by the truth table of Table II represents theimplementation of the lookup table and the coefficient values based onthe memory address and memory content columns of Table I. In Table II,ACCMSBD represents the output signal of register 414, and I/Q XD and I/QYD represent the corresponding outputs of the shift registers 444I and444Q of the two stage I Channel input data (symbol) shift register 440Iand the two stage I Channel input data (symbol) shift register 440Q. Thelogic in the truth table also includes the combination of both I and Qchannel lookups in a single set of 4 coefficient tables rather than onefor each (i.e. the coefficient memories are timeshared between the twochannels). After the coefficient address generator 416 counts up to themid-range value (in Table I the mid-range is eight counting zero toseven), the XOR array 412 of the coefficient address generator 416performs an exclusive or logic operation of the most significant bitwith the current address count and then counts down the address becauseonly thirty-two values (eight values in Table I) for each coefficientare required. The additional bit which is concatenated on to the fivebits in the circuit 400 designed for 64 samples per symbol bit (threebits in the Table I example designed for 16 samples per symbol bit)represents a control bit that selects the desired pair of coefficientvalues from the memory (i.e. either C0x+C0y or C0x−C0y) based on whetherthe data symbol for I0 is the same or different from I7. If the datasymbol for I0 is the same as I7, C0x+C0y is selected and if data symbolfor I0 is different from I7, C0x−C0y is selected. Then the SELI07 orSELQ07 is used as determined by the truth table logic of Table II toselect either the positive or negative coefficient value for either theI or Q channel. The baseband bit shaping techniques can also be used fordigital low pass filters having with symmetric coefficients.

All publications and references cited herein are expressly incorporatedherein by reference in their entirety.

Having described the preferred embodiments of the invention, it will nowbecome apparent to one of ordinary skill in the art that otherembodiments incorporating their concepts may be used. It is felttherefore that these embodiments should not be limited to disclosedembodiments but rather should be limited only by the spirit and scope ofthe appended claims.

1. A method for shaping a baseband signal comprising: providing aplurality of coefficient memories, each having a plurality ofcoefficients values representing filter response waveform values;determining a coefficient memory address for each of the coefficientmemories; addressing each of the plurality of coefficient memories;retrieving an addressed coefficient value from each of the plurality ofcoefficient memories; providing a negative value for each of theretrieved ones of the plurality of coefficient values; selecting inresponse to the baseband signal for each coefficient value, one of theretrieved coefficient value and the negative value; and summing theselected values for providing a shaped signal; wherein coefficientvalues at an instance in time are each indicative by a digital word andwherein one of the digital words and a corresponding negative value ofthe digital word are selected in response to the baseband signal, andthe selected digital words are summed for providing a shaped basebandsignal.
 2. The method of claim 1 further comprising sharing theplurality of coefficient memories for shaping both an in-phase basebandsignal and a quadrature baseband signal.
 3. The method of claim 2wherein sharing the plurality of memories comprises: retrieving one ofthe coefficient values corresponding to the in-phase baseband signal ona first edge of a clock signal; and retrieving one of the coefficientvalues corresponding to the quadrature baseband signal on a differentsecond edge of the clock signal.
 4. The method of claim 3 wherein theclock signal comprises a digital to analog converter clock signal. 5.The method of claim 1 wherein determining a coefficient memory addresscomprises: determining an increment for providing a predetermined numberof samples for each of a plurality of symbols comprising the basebandsignal; and incrementing an address counter in response to thepredetermined number of samples for each symbol and a predeterminedcoefficient memory size.
 6. The method of claim 1 wherein the basebandsignal comprises an in-phase signal and a quadrature signal; whereinselecting for each coefficient value comprises selecting an in-phasevalue in response to the in-phase signal and selecting a quadraturevalue in response to the quadrature signal; and wherein summing theselected values comprises summing the selected in phase values forproviding a shaped in phase signal and summing the selected quadraturevalues for providing a shaped quadrature signal.
 7. The method of claim1 wherein the negative value comprises at least one of: a 2's complementvalue; an offset binary value; and a signed magnitude value.
 8. Themethod of claim 1 wherein providing a plurality of coefficient memoriescomprises combining at least two filter coefficients for forming theplurality of coefficient values such that coefficient memory storage isminimized.
 9. The method of claim 1 wherein the plurality of coefficientmemories provided further provide coefficient values corresponding to aplurality of roll-off factors.
 10. The method of claim 1 wherein theplurality of coefficient memories further includes one of: the sum of afirst filter response value and a second filter response value; and thedifference of a first filter response value and a second filter responsevalue; and wherein the step of retrieving an addressed coefficient valueretrieves one of the sum of a first filter response value and a secondfilter response value and the difference of a first filter responsevalue and a second filter response value.
 11. The method of claim 10wherein the first filter response and the second filter response aresymmetric.
 12. The method of claim 10 wherein retrieving coefficientvalues comprises: providing an address counter having a plurality oflogic outputs for addressing the coefficient memories; and determiningfor each coefficient memory whether to retrieve one of the sum of afirst filter response value and a second filter response value and thedifference of a first filter response value and a second filter responsevalue in response to selected ones of the logic outputs.
 13. The methodof claim 12 further comprising: providing a logic circuit having anoutput, a first input coupled to a logic output of the address counter,a second input coupled to an in-phase data symbol bit and a third inputcoupled to a quadrature data symbol bit; determining whether to selectone of the retrieved value and the negative value in response to theoutput of the logic circuit.
 14. The method of claim 10 wherein summingthe selected value comprises: providing a plurality of adder stages,each adder coupled to a pipeline register; clocking the pipelineregister at a digital to analog converter (D/A) rate; and scaling andformatting the summed values after a final adder stage.
 15. A method forshaping a baseband signal comprising: providing a plurality ofcoefficient memories, each having a plurality of coefficients valuesrepresenting filter response waveform values; determining a coefficientmemory address for each of the coefficient memories; addressing each ofthe plurality of coefficient memories; retrieving an addressedcoefficient value from each of the plurality of coefficient memories;providing a negative value for each of the retrieved ones of theplurality of coefficient values; selecting in response to the basebandsignal for each coefficient value, one of the retrieved coefficientvalue and the negative value; and summing the selected values forproviding a shaped signal; and wherein the plurality of coefficientmemories further includes one of the sum of a first filter responsevalue and a second filter response value and the difference of a firstfilter response value and a second filter response value; and whereinthe baseband signal is clocked at a symbol rate and the retrieval ofcoefficients is clocked at a digital to analog converter (D/A) rate suchthat the number of retrievals per coefficient equals the D/A ratedivided by the symbol rate.
 16. The method of claim 10 wherein thefilter waveform comprises a raised cosine.
 17. The method of claim 10wherein the filter waveform comprises a square root raised cosine. 18.The method of claim 1 further comprising combining at least two filtercoefficients for forming the plurality of coefficient values indicatedby each digital word such that coefficient memory storage is minimized.19. A device comprising: a plurality of coefficient memories, eachmemory having an input address bus, a multiplexor input and acoefficient value output; a plurality of first registers, each having adigital to analog (D/A) clock input and an input coupled to a respectiveone of the coefficient value outputs, and an output; a plurality ofnegative value circuits, each circuit having an input coupled to arespective one of the first register outputs, and an output; a pluralityof 2:1 multiplexors, each having a first input coupled to an output of arespective one of the plurality of first registers and having a secondinput coupled to an output of a respective one of the plurality ofnegative value circuits; a plurality of second registers, each having adigital to analog (D/A) clock input and an input coupled to a respectiveone of the outputs of the plurality of 2:1 multiplexors, and an output;and an adder having a plurality of inputs coupled to respective ones ofthe plurality of second registers and an output to provide a basebandsignal; wherein coefficient values at an instance in time are eachindicative by a digital word and wherein one of the digital words and acorresponding negative value of the digital word are selected inresponse to the baseband signal and the selected digital words aresummed to provide the baseband signal.
 20. The device of claim 19wherein each of the plurality of negative value circuits comprises atleast one of: a 2's complement logic element; an offset binary logicelement; and a signed magnitude logic element.
 21. The device of claim19 further comprising a coefficient address generator having an outputcoupled to a coefficient memory input address bus, the input addresshaving a plurality of address lines.
 22. A device comprising: aplurality of coefficient memories, each memory having an input addressbus, a multiplexor input and a coefficient value output; a plurality offirst registers, each having a digital to analog (D/A) clock input andan input coupled to a respective one of the coefficient value outputs,and an output; a plurality of negative value circuits, each circuithaving an input coupled to a respective one of the first registeroutputs, and an output; a plurality of 2:1 multiplexors, each having afirst input coupled to an output of a respective one of the plurality offirst registers and having a second input coupled to an output of arespective one of the plurality of negative value circuits; a pluralityof second registers, each having a digital to analog (D/A) clock inputand an input coupled to a respective one of the outputs of the pluralityof 2:1 multiplexors, and an output; an adder having a plurality ofinputs coupled to respective ones of the plurality of second registers;and a coefficient address generator having an output coupled to acoefficient memory input address bus, the input address having aplurality of address lines; and wherein the coefficient addressgenerator further comprises: an adder having a plurality of addressoutput lines; an address register coupled to the plurality of addressoutput lines and having clocked address line outputs and an addresscounter most significant bit output; an exclusive or logic gate (XOR)array having address inputs coupled to the clocked address lines outputsand an address counter most significant bit input coupled to the addresscounter most significant bit output, and outputs coupled to acorresponding plurality of the plurality of address lines of thecoefficient memory address bus; and an XOR multiplexor having inputscoupled a pair of baseband bit signals and an output coupled to one ofthe plurality of address lines of the coefficient memory address bus.